emb4fun

I wanted to use lwIP on a board that has two ethernet interfaces. For this reason I used the MIMXRT1160-EVK and MIMXRT1170-EVK board. As a special feature, the board has a 10/100 Mbit/s and a 1 Gbit/s interface. This made me curious what kind of performance can be achieved with lwIP and TinyCTS on the 1Gbit/s interface while also considering the CPU load. For the compiler SEGGER Embedded Studio for ARM was used here.

For the measurements iperf v2.1.8 was used in the terminal on a Mac. The computer and the evaluation board are connected to each other via a 1GBit switch. The CPU load of the target can be checked in the terminal of the target by pressing "c".

Btw, sometimes it is better not to trust the debugger and power off/on the target ;o)

One more note about lwIP in this example. Instead of the lwIP internal allocator an own malloc/free system based on the SDRAM is used. The NoCache area will be used for the DMA data.

I have tried to achieve the maximum data transfer here. If this was not possible with one iperf stream additional streams was used. Compared to the original NXP lwIP example driver, the input function of lwIP will not be called inside an interrupt. Here a semaphore will be used inside the interrupt, and the input function will be called in a task. This example doesn't run with ZeroCopy, as I haven't been able to get it to work with my sources. The CPU load values are approximate values and could fluctuate a few percent up and down.

Code	QSPI	QSPI	ITCM	ITCM	SDRAM	SDRAM
Data	DTCM	DTCM	DTCM	DTCM	SDRAM	SDRAM
NoCache	OCRAM	SDRAM	OCRAM	SDRAM	OCRAM	SDRAM
Streams	1	1	1	1	1	1
Mbit/s	94	94	94	94	94	94
CPU load (%)	96	99	23	31	40	48

Code	QSPI	QSPI	ITCM	ITCM	SDRAM	SDRAM
Data	DTCM	DTCM	DTCM	DTCM	SDRAM	SDRAM
NoCache	OCRAM	SDRAM	OCRAM	SDRAM	OCRAM	SDRAM
Streams	2	2	3	3	2	2
Mbit/s	183	152	429	304	276	214
CPU load (%)	93	92	97	95	96	93

Note: During the tests with the QSPI, I got different values when I reset the board by pressing the reset button or with a power cycle (off/on). For example, the values were 81 Mbit/s with a reset and 94 Mbit/s with a power cycle. This is a strange behavior and requires further investigation later.

Code	QSPI	QSPI	ITCM	ITCM	SDRAM	SDRAM
Data	DTCM	DTCM	DTCM	DTCM	SDRAM	SDRAM
NoCache	OCRAM	SDRAM	OCRAM	SDRAM	OCRAM	SDRAM
Streams	1	1	1	1	1	1
Mbit/s	91	87	92	93	92	92
CPU load (%)	97	98	15	21	32	41

Code	QSPI	QSPI	ITCM	ITCM	SDRAM	SDRAM
Data	DTCM	DTCM	DTCM	DTCM	SDRAM	SDRAM
NoCache	OCRAM	SDRAM	OCRAM	SDRAM	OCRAM	SDRAM
Streams	1	1	3	4	2	2
Mbit/s	120	108	536	334	297	228
CPU load (%)	95	93	79	93	88	88

This project here is for me more than only a Proof of Concept. It could be a starting point for a lwIP application where more than one ethernet interfaces are needed. At the same time, it makes me curious how the performance can be increased by using the ZeroCopy functionality.