sdram
altera_avalon_new_sdram_controller v15.0
Parameters
| TAC |
5.5 |
| TRCD |
20.0 |
| TRFC |
70.0 |
| TRP |
20.0 |
| TWR |
14.0 |
| casLatency |
3 |
| columnWidth |
9 |
| dataWidth |
16 |
| generateSimulationModel |
false |
| initRefreshCommands |
8 |
| model |
single_Micron_MT48LC4M32B2_7_chip |
| numberOfBanks |
4 |
| numberOfChipSelects |
1 |
| pinsSharedViaTriState |
false |
| powerUpDelay |
200.0 |
| refreshPeriod |
7.8125 |
| rowWidth |
13 |
| masteredTristateBridgeSlave |
0 |
| TMRD |
3 |
| initNOPDelay |
0.0 |
| registerDataIn |
true |
| clockRate |
100000000 |
| componentName |
qsys_core_sdram |
| size |
33554432 |
| addressWidth |
24 |
| bankWidth |
2 |
| deviceFamily |
UNKNOWN |
| generateLegacySim |
false |
|
Software Assignments
| CAS_LATENCY |
3 |
| CONTENTS_INFO |
|
| INIT_NOP_DELAY |
0.0 |
| INIT_REFRESH_COMMANDS |
8 |
| IS_INITIALIZED |
1 |
| POWERUP_DELAY |
200.0 |
| REFRESH_PERIOD |
7.8125 |
| REGISTER_DATA_IN |
1 |
| SDRAM_ADDR_WIDTH |
24 |
| SDRAM_BANK_WIDTH |
2 |
| SDRAM_COL_WIDTH |
9 |
| SDRAM_DATA_WIDTH |
16 |
| SDRAM_NUM_BANKS |
4 |
| SDRAM_NUM_CHIPSELECTS |
1 |
| SDRAM_ROW_WIDTH |
13 |
| SHARED_DATA |
0 |
| SIM_MODEL_BASE |
0 |
| STARVATION_INDICATOR |
0 |
| TRISTATE_BRIDGE_SLAVE |
"" |
| T_AC |
5.5 |
| T_MRD |
3 |
| T_RCD |
20.0 |
| T_RFC |
70.0 |
| T_RP |
20.0 |
| T_WR |
14.0 |
|