Small examples


These examples can be used for a starting point for your own work with the NEORV32.
I will provide you some examples such as:

  • Blinky
  • SDRAM access directly via the Wishbone bus
  • SDRAM access via the Wishbone to Avalon master in the Qsys area

Some NEORV32 examples for Intel FPGA boards using Quartus and SEGGER Embedded Studio for RISC-V. A description of how to use Embedded Studio for RISC-V can be find here.

This examples use the Quartus II software version 15.0.2 and the NEORV32 v1.6.5.


For these examples the following Terasic boards was used:





Cyclone V GX Starter Kit

"JTAG Terasic Adapter"

Board pictures by Terasic

The JTAG connection for debugging can either be established via a simple wire connection, or you can use a small adapter such as the "JTAG Terasic Adapter".

Some specifications for the NEORV32 application and the board used:

Board Familiy clk_i IMEM DMEM SDRAM
DE10-Lite MAX10 90 MHz 64KB 32KB 64MB
DE1 Cyclone II 50 MHz 16KB 8KB 8MB
DE0-Nano Cyclone IV 100 MHz 32KB 16KB 32MB
DE0-CV Cyclone V 100 MHz 128KB 64KB 64MB
Cyclone V GX Starter Kit Cyclone V GX 90 MHz 256KB 128KB 0MB


Quartus neorv32-examples_20220101 project (6.68 MB)

There is also my neorv32-examples repository available on GitHub.