DE0-Nano reference
Address Map
J-Flash SPI
Debug, TCM / SDRAM

This project is still under construction.


It is not the reference but my reference. That means it includes the parts that I find important for my tests here. Others will certainly find other parts more important. But that is the nice thing about the NEORV32 project, here everyone can put their system together as they need it.

And why the DE0-Nano and not the XYZ board? Compared to my other boards, the DE0-Nano is the cheapest board, and it is easier to use the second connector if the JTAG adapter is used on the other one.


Here a DE0-Nano board with "JTAG Terasic Adapter" and SPI Flash was used:

The DE0-Nano provides a lot of functionality. But only the following subset was used:

  • Cyclone IV (EP4CE22F17C6)
  • Build in USB Blaster
  • 32 MByte SDRAM
  • 2 Push-button switches
  • 8 Green User LEDs
  • 50 MHz oscillator
  • Additional SPI Flash (IS25LP032D, on the JTAG adapter)

The following options of the NEORV32 have been enabled:

  • Bootloader
  • On-Chip Debugger
  • Internal Instruction memory
  • Internal Data memory
  • Internal Cache memory
  • External memory interface
  • GPIO
  • SPI
  • UART0
  • Machine System Timer

Address Map

The settings on the NEORV32 result in the following address map:

 Peripheral  Address Offset  Size (bytes)  Attribute
 SYSINFO  0xFFFFFFE0  32  System Information Memory
 GPIO  0xFFFFFFC0  16  General Purpose Input / Output
 SPI  0xFFFFFFA8  8  Serial Peripheral Interface
 UART0  0xFFFFFFA0  8  Primary UART
 MTIME  0XFFFFFF90  16  Machine System Timer
 On-Chip Debugger  0xFFFF8000  512  OCD address space
 Bootloader ROM  0xFFFF0000  4K  Bootloader address space
 SDRAM  0x90000000  32M  External SDRAM
 DMEM  0x80000000  16K  On-chip Data memory
 iMEM  0x00000000  32K  On-chip Instruction memory

J-Flash SPI

Unfortunately the J-Link EDU lacks the license for J-Flash SPI. If you have access to a J-Link with the right license, there is a project in the download area (de0n-spi) that connects the SPI Flash of
the "JTAG Terasic Adapter" directly to the JTAG.

Debug, TCM / SDRAM



Quartus de0n-spi_20211229 project for the direct JTAG to SPI connection (16 KB)

de0n-spi.sof which simply has to be loaded into the FPGA with the programmer (687 KB)

This project is still under construction.