Introduction

Xilinx Virtual Cable (XVC) is a TCP/IP-based protocol that acts like a JTAG cable and provides a means to access and debug your FPGA or SoC design without using a physical cable.

This capability helps facilitate hardware debug for designs that:

• Have the FPGA in a hard-to-access location, where a "lab-PC" is not close by.

• Do not have direct access to the FPGA pins, e.g. the JTAG pins are only accessible via a local processor interface.

• Need to efficiently debug Xilinx FPGA or SoC systems deployed in the field to save on costly or impractical travel and reduce the time it takes to debug a remotely located system.

(Source: GitHub Xilinx)

Or, as in the example here, the XVC can also be used as a replacement for a Xilinx USB Platform Cable or Digilent USB-JTAG circuitry.

Hardware

Here a Digilent Arty A7-35T board was used. In general the board is equipped with a onboard Digilent USB-JTAG circuitry. But for this tutorial this functionality will not be used.

Note: It is important if you follow this tutorial, the board must NOT powered by the USB port J10. The board must be powered by the Power jack for external supply.

However, if the USB port J10 is used, the signals from the onboard Digilent USB-JTAG circuitry and the J-Link drive against each other. In this case something can be damaged.

Here the J-Link is connected to J8 of the Arty A7 board:

Software

At the time of writing this tutorial, the following software was installed:

• J-Link Software v7.92e
• Xilinx Vivado 2019.1

The J-Link XVCD Server is part of the J-Link software package (starting with v7.92e). A detailed description of the J-Link XVCD server can be found here.

Before starting the J-Link XVCD Server make sure a J-Link is connected to the computer and the target device is powered and connected to the J-Link. After successfull connection with the J-Link, the server will waiting for a connection and the the output will looks like:

As an example there is a HDL Blinky for the Arty Board. It was created with v2019.1 of Vivado. Start Vivado and open the Blinky example. Create the Bitstream of the example and open the Hardware Manager. Click "Auto Connect" to start a connection:

In our case it will not create a connection at this point, because no compatible "Xilinx USB Platform Cable" is connected. Right click "localhost" and select "Add Xilinx Virtual Cable (XVC)...":

Use "localhost" for the "Host name" and "2542" for the "Port":

Press "OK" and a connection will be established:

The device can now be programed with "Program device":

Select the Bitstream file and press "Program":

Now the Bitstream will be programed with the help of the J-Link XVCD Server into the target. After that there is a chaser with LD4 to LD7.

When Vivado is closed, the connection to the J-Link XVCD server is also closed:

Download

Arty A7 Blinky tested with an Arty A7-35T development board (Artix-7)