/**************************************************************************** * Copyright (c) 2011 by Michael Fischer. All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * 3. Neither the name of the author nor the names of its contributors may * be used to endorse or promote products derived from this software * without specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL * THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF * THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. * ***************************************************************************** * History: * * 06.11.2011 mifi First Version, for the Nios II tutorial. * The tutorial can be find here: * http://www.emb4fun.de * * 23.11.2011 mfi Rework, change Nios II clock to 100 MHz and * added UART. ****************************************************************************/ /*=========================================================================*/ /* DEFINE: The module */ /*=========================================================================*/ module de1_chibios ( /* * Input clock */ CLOCK_50, /* * SDRAM interface, * here a A3V64S40ETP-G6 (166MHz@CL-3) is used. * Reference is made to Zentel datasheet: * A3V64S40ETP, Revision 1.2, Mar., 2010 */ SDRAM_CLK, // Master Clock SDRAM_CKE, // Clock Enable SDRAM_CS_N, // Chip Select SDRAM_RAS_N, // Row Address Strobe SDRAM_CAS_N, // Column Address Strobe SDRAM_WE_N, // Write Enable SDRAM_DQ, // Data I/O (16 bits) SDRAM_DQML, // Output Disable / Write Mask (low) SDRAM_DQMU, // Output Disable / Write Mask (high) SDRAM_ADDR, // Address Input (12 bits) SDRAM_BA_0, // Bank Address 0 SDRAM_BA_1, // Bank Address 1 /* * LEDs, green and red */ LED_GREEN, LED_RED, LED_HEARTBEAT, /* * Swithes and keys */ KEY, SW, /* * 7-segment display */ SEG7, /* * UART_0 */ UART_TXD, UART_RXD ); /*=========================================================================*/ /* DEFINE: Input / Output */ /*=========================================================================*/ input CLOCK_50; output SDRAM_CLK; // Master Clock output SDRAM_CKE; // Clock Enable output SDRAM_CS_N; // Chip Select output SDRAM_RAS_N; // Row Address Strobe output SDRAM_CAS_N; // Column Address Strobe output SDRAM_WE_N; // Write Enable inout [15:0] SDRAM_DQ; // Data I/O (16 bits) output SDRAM_DQML; // Output Disable / Write Mask (low) output SDRAM_DQMU; // Output Disable / Write Mask (high) output [11:0] SDRAM_ADDR; // Address Input (12 bits) output SDRAM_BA_0; // Bank Address 0 output SDRAM_BA_1; // Bank Address 1 output [7:0] LED_GREEN; output [8:0] LED_RED; output LED_HEARTBEAT; input [3:0] KEY; input [9:0] SW; output [27:0] SEG7; output UART_TXD; input UART_RXD; /*=========================================================================*/ /* DEFINE: Definition of all local variables */ /*=========================================================================*/ wire CLK_SYS; wire CLK_10; wire pll_locked; /*=========================================================================*/ /* DEFINE: All HDL code */ /*=========================================================================*/ /* * pll_sys, created during section "System PLL". * For more information take a look here: * * http://www.yagarto.de/howto/niosii/niosii1/index.html#pll * */ pll_sys pll_sys_inst ( .inclk0(CLOCK_50), /* in: 50 MHz */ .c0(CLK_SYS), /* out: 100 MHz */ .c1(SDRAM_CLK), /* out: 100 MHz */ .c2(CLK_10), /* out: 10 MHz */ .locked(pll_locked) ); /* * de1_sopc, created during section "Nios II - SOPC". * For more information take a look here: * * http://www.yagarto.de/howto/niosii/niosii1/index.html#sopc * */ de1_sopc de1_sopc_inst ( .clk_sys(CLK_SYS), .zs_addr_from_the_sdram(SDRAM_ADDR), .zs_ba_from_the_sdram({SDRAM_BA_1,SDRAM_BA_0}), .zs_cas_n_from_the_sdram(SDRAM_CAS_N), .zs_cke_from_the_sdram(SDRAM_CKE), .zs_cs_n_from_the_sdram(SDRAM_CS_N), .zs_dq_to_and_from_the_sdram(SDRAM_DQ), .zs_dqm_from_the_sdram({SDRAM_DQMU,SDRAM_DQML}), .zs_ras_n_from_the_sdram(SDRAM_RAS_N), .zs_we_n_from_the_sdram(SDRAM_WE_N), .out_port_from_the_pio_led_green(LED_GREEN), .out_port_from_the_pio_led_red(LED_RED), .out_port_from_the_pio_7seg(SEG7), .in_port_to_the_pio_sw(SW), .in_port_to_the_pio_key(KEY), .rxd_to_the_uart_0(UART_RXD), .txd_from_the_uart_0(UART_TXD), .reset_n(pll_locked) ); simple_counter simple_counter_inst ( .clock(CLK_10), .counter_out(LED_HEARTBEAT) ); endmodule /*** EOF ***/